ABSTRACT

             The report is based on the Digital Implementation of Phase locked loop on FPGA, the report covers the steps taken for implementing the proposed Phase Locked loop architecture on the FPGA. The building blocks used for the architecture are explained in detail as well as the software and technologies used for the project. An extensive literature research has also been done on past designs of the PLL and its contribution to this project is explained. Finally, the results gotten from the software and hardware will also be analysed.

TABLE OF CONTENTS

DECLARATION STATEMENT

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ABSTRACT

ACKNOWLEDGEMENTS

TABLE OF CONTENTS

LIST OF FIGURES

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LIST OF TABLES

GLOSSARY

1. INTRODUCTION

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1.1 AIMS AND OBJECTIVES

2. LITERATURE REVIEW

2.1. BUILDING BLOCKS OF PHASE LOCKED LOOP

2.1.1. PHASE DETECTOR

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2.1.2. LOW PASS FILTER

2.1.3    VOLTAGE CONTROLLED OSCILLATOR

2.2. TYPES OF PHASE LOCKED LOOP

2.3. TECHNOLOGY AND DESIGN TOOLS

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2.3.1. FPGA NANOBOARD

2.3.2. XILINX SYSTEM GENERATOR FOR DSP

2.4. FPGA BASED PLL BASED ON RANDOM SAMPLING

2.4.1. OVERVIEW

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2.4.2. ARCHITECTURE OF PROPOSED DESIGN

2.4.3. IMPLEMENTATION OF EACH BLOCK

2.4.4. TESTING AND RESULTS

2.5. FPGA BASED PLL WITH WIRELESS TRANSCEIVER   ARCHITECTURE TESTING

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2.5.1. OVERVIEW

2.5.2. ARCHITECTURE OF PLL

2.5.3. IMPLEMENTATION

2.5.4. TESTING

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2.5.5. ANALYSIS OF RESULTS

2.6. COMPARISON OF CASE STUDIES

2.7. CONTRIBUTIONS TO CURRENT WORK

2.8. NUMERICALLY CONTROLLED OSCILLATOR

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2.8.1. OVERVIEW

2.8.2. CORDIC BASED NCO

2.8.3. IIR FILTER BASED NCO

2.8.4. LUT BASED NCO

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3. SYSTEM DESIGN AND TESTING

3.1. OVERVIEW

3.2. PROPOSED SYSTEM ARCHITECTURE

3.2.1. PHASE DETECTOR

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3.2.2. DIGITAL FILTER

3.2.3. NUMERICALLY CONTROLLED OSCILLATOR

3.3. TESTING OF EACH BLOCK

3.3.1. OVERVIEW

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3.3.2. DIGITAL FILTER TEST

3.3.3. PHASE DETECTOR TEST

3.3.4. NUMERICALLY CONTROLLED OSCILLATOR TEST

4. RESULTS AND ANALYSIS

4.1. OVERVIEW

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5. CONCLUSION

6. FURTHER DEVELOPMENT

REFERENCES

BIBLIOGRAPHY

APPENDIX A: PROPOSED PLL DESIGN

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APPENDIX B: DIGITAL FILTER TEST DESIGN

APPENDIX C: PHASE DETECTOR TEST DESIGN

APPENDIX D: NUMERICALLY CONTROLLED OSCILLLATOR TIME DOMAIN TEST

LIST OF FIGURES

Figure 1: Basic Structure of Phase locked Loop

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Figure 2: Xilinx FPGA

Figure 3: Design Flow for System generator for DSP

Figure 4: Logical Diagram of 16-Bit pseudo-random number generator

Figure 5: Fixed input frequency test, Output frequency (a, b, c) and LD signals for three different loop bandwidth [14].

Figure 6: Square Wave input frequency test. [14]

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Figure 7: Sinusoidal input frequency test [14]

Figure 8: Simulink model of the ADPLL [12]

Figure 9: Proposed design of phase detector and loop filter

Figure 10: Simulated results of the ADPLL design[12].

Figure 11: Simulated Result for the NCO outputs I_feedback and Q_feedback [12].

Figure 12: The ADPLL set up [12].

Figure 13: I-Q constellation transmitted with the input signal of 2.4 GHz [12]

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Figure 14: I-Q constellation recovered by the proposed ADPLL with the input signal of 2.4 GHz [12]

Figure 15: CORDIC Vector Rotation Diagram

Figure 16: 2nd order IIR Filter for generating sine wave

Figure 17: Block Diagram for LUT Based NCO[19].

Figure 18: Flow Chart describing whole project

Figure 19: Proposed Architecture of PLL

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Figure 20: Response Curve for XOR Phase Detector [16].

Figure 21: Subsystem of Proposed NCO

Figure 22: Digital Filter test schematic

Figure 23: Output of Digital Filter with a 1Hz Input Signal

Figure 24: Phase Detector testing schematic

Figure 25: input signals with equivalent phases;

Figure 26: Difference in phase between the two input signals

Figure 27: Output of the PLL (Input Signal and Generated output signal)

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Figure 28: Spectrum analyser view of the NCO output

LIST OF TABLES

Table 1: Parameter Values of Digital Filter

Table 2: Parameter values of two input signals

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Table 3: Table Comparison between Input Signal and NCO output

GLOSSARY

1.   INTRODUCTION

Phase Locked loop is a control system which has an input signal that is synchronized in frequency and phase with a generated output signal gotten from a control oscillator. This means the PLL will be in a locked condition when the input signal and the output signal have zero or very small difference between there frequency and phase. Phase locked loop usually comprises of voltage controlled oscillator, phase detector or comparator and a low pass filter. The oscillator produces a periodic signal. The phase detector compares the phase of the input periodic signal with the phase of the produced/generated periodic signal and modifies the oscillator to keep the phases synchronized. The PLL is classified as a feedback loop system due to the fact that it takes an output signal towards the input signal for a comparison in a loop.

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PLL’s are used in a variety of applications such as AM and FM Modulation, Frequency multiplication, Clock distribution and recovery and also jitter and noise reduction. They are also used in demodulating a signal, recovering a signal from a noisy communication channel and generate a stable frequency at multiples of an input frequency or distribute precisely timed clock pulses in digital logic circuits , for example a microprocessor [1].

1.1        AIMS AND OBJECTIVES

The sole aim of this project is to design a digitally based phased locked loop which can be implemented on an FPGA, the preferable type of PLL to use in this case is the All-Digital PLL which was discussed earlier. The reason being is due to the fact that all building blocks are digitally based. The aim of this report is to explain in details how the All-Digital PLL was modelled on Xilinx System Generator for DSP software and how it was eventually synthesized onto the FPGA. The project workload has been subdivided into various objectives which includes;

• Choosing the appropriate software
• Choosing the appropriate software blocks for the design
• Modelling the All-Digital Based PLL
• Setting the appropriate parameter units
• Testing the chosen software blocks
• Implementation and synthetisation of design on FPGA

2.   LITERATURE REVIEW

An extensive literature research has been performed on the phase locked loop and it has been seen that its building blocks have various ways it could be implemented and also different digital and analog counterparts. This section will take an in-depth analysis of each of these blocks which will include the theory behind each of them, case studies, equations and diagrams etc. This section will also take an analysis of some related case studies and its contribution to the current project. An explanation on the devices required for the project have also been covered.

2.1.         BUILDING BLOCKS OF PHASE LOCKED LOOP

The typical phase locked loop has three main building blocks in the design as stated in section 1. These blocks are mainly;

1. Phase Detector
2. Low pass Filter
3. Voltage Controlled Oscillator

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2.1.1.               PHASE DETECTOR

This is the part of the PLL that is responsible for the comparing of the input signal and the generated output signal to determine whether or not both signals have similar phase and frequencies. This part of the PLL has the most significance due to the fact that is solely responsible for determining the phase difference in the loop and it also detects the resulting error in the PLL if there is any. In order for a better understanding of this block, assume there is a frequency of any random value, if the Fin≠ Fgen, the phase-error signal, after being filtered and amplified, causes the generated frequency to deviate in the direction of the of Fin[2]. If the conditions are right, the generated frequency will quickly lock to Fin, maintaining a fixed phase relationship with the input signal [2].

2.1.2.               LOW PASS FILTER

This part of the PLL will remove unnecessary high frequencies which could pass out of the phase detector and go through the VCO. From Figure 1-1, it is seen that there is a reference signal in the block diagram which contains sum and difference frequency components which are often times called high and low frequency components respectively. The PLL will only require the high frequency components and it is the duty of the low pass filter to cut-off the low frequency components from the phase detector so the signal can be passed to the VCO. Thereafter, the input signal and reference signal will be locked in phase and frequency

2.1.3    VOLTAGE CONTROLLED OSCILLATOR

This block will feed the generated output signal to the phase detector to determine whether it is in phase with the input signal. The frequency of the output signal of the VCO is controlled by the input voltage driven into it. This input voltage will define the oscillation frequency. Consequently, modulated signals connected to the input signals may cause frequency modulation (FM) or phase modulation (PM). VCO can have a sine wave, square wave, ramp wave as its output but it’s solely dependent on the input signal driven into the phase locked loop. Analog based phase locked loop normally uses the VCO while the digitally based phase locked loop contains the VCO’s digital counterpart called a Numerically Controlled Oscillator (NCO) or in a semi-digital phase locked loop called a Digitally Controlled Oscillator (DCO).

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2.2.         TYPES OF PHASE LOCKED LOOP

There are different variations of the phase locked loop which can have either analogically or digitally based building blocks, these include;

• Digital PLL: Building blocks include an analog based VCO and low pass filter and a digital phase detector including XOR and Phase frequency detector
• Analog PLL: All analog based building blocks with a an analog multiplier used as the phase detector
• All-Digital PLL: All building blocks are digitally based and uses a numerically controlled oscillator (NCO) instead of a VCO. 
• Software PLL: All blocks are implemented on a software rather than a hardware e.g. MATLAB

2.3.         TECHNOLOGY AND DESIGN TOOLS

2.3.1.             FPGA NANOBOARD

The term FPGA stands for Field Programmable Gate Array. An FPGA is an integrated circuit system which can be programmed or configured to the required functionality of the user. They are widely used in many industries for different purposes such as digital signal processing, media imaging, speech recognition, consumer electronics, military and aerospace. Due to these various applications this makes the FPGA more economical and marketable. Different companies such Xilinx Inc., Lattice Semiconductor and Altera Corporation are some of the top leading manufactures and accounted for more than 80% of the global FPGA market share in 2014[3].

The internal structure of an FPGA contains a programmable logic blocks such as AND & XOR, I/O cells which connects the logic cells to external signals and a programmable routing network interconnecting the cells. The FPGA are programmed using Hardware Description language such as Verilog and VHDL.

Figure 2: Xilinx FPGA

2.3.2.             XILINX SYSTEM GENERATOR FOR DSP

System Generator is a DSP design tool from Xilinx that uses MathWorks model based Simulink design environment for FPGA design [7]. Past experience with Xilinx FPGA or RTL design approaches are not requires when utilizing system generator. Designers can develop and simulate a model using MATLAB, Simulink and Xilinx library of bit or cycle-true models. Xilinx pre-advanced algorithm are then mapped from the synthesizable hardware description language (HDL) which are made automatically from the tool. The HDL design will then be integrated for implementation on Xilinx FPGA and any other programmable SoCs. Subsequently, designers can characterize conceptual representation of a system-level design and effortlessly change this single source code into a gate level portrayal. Also, it gives a programmed generation of a HDL test bench, which can enable design to be verified after implementation. The figure below is a flow chart that summarizes the flow of a Simulink design to the implementation to the FPGA.

Figure 3: Design Flow for System generator for DSP

The level of abstraction given by System Generator for DSP has significantly clarified algorithm development. Besides the system-level modelling library, System generator incorporates a code generator that can automatically produces a synthesizable VHDL netlist from a Simulink model.  This netlist contains IP (Intellectual property) that have been designed specifically for high level performance and density in Xilinx FPGA. System generator creates project and constraints file to assist implementation using Xilinx foundation as the major synthesis tool [11].

2.4.         FPGA BASED PLL BASED ON RANDOM SAMPLING

2.4.1.               OVERVIEW

It is well known that digitally based PLL are only compatible with low frequency based applications and cannot be processed with high frequency based applications. This is due to the fact that at high frequencies, there are a lot of mathematical calculations which restricts the functioning in a DSP system. Also the analog to digital converter (ADC) restricts the speed of DSP systems [4]. The proposed PLL based on random sampling is brought about by the idea of been able to use random sampling to process high frequency analog signals at frequencies lower than the Nyquist frequency without having an aliasing effect. Aliasing effect on a signal occurs when a signal is been sampled at a frequency similar or even smaller than the signal being measured.

2.4.2.               ARCHITECTURE OF PROPOSED DESIGN

The PLL in this section follows the typical concept of a basic PLL were the components are the input signal, phase detector (PD), the loop filter, VCO and output signal. A sine wave is used as the input signal of the design. The phase detector generates a signal formed by the phase error which is added by other non-desired parts, for example, the high frequency harmonics originating from the non-linear components (i.e. multiplication) and arbitrary noise. The filter will sift out these redundant components and will just keep the phase error signal. The filter also functions as a controller in the closed loop system, which attempts to decrease the phase error signal to zero. The Proportional Integral (PI) is a good example of a filter that meets these necessities. The gain constants within the PI design can determine how far the locking time is and the range between each period of the output signal.

The sampling type methodology used in this design is called Addictive random sampling (ARS). This is a type of sampling methodology intended to provide alias-free processing of random signals [13]. The input signal driven into the phase detector of the proposed design is sampled at random moments which are characterised by the equation shown below;